This project work titled DESIGN OF A FULL ADDER CIRCUIT has been deemed suitable for Final Year Students/Undergradutes in the Electrical & Electronics Department. However, if you believe that this project work will be helpful to you (irrespective of your department or discipline), then go ahead and get it (Scroll down to the end of this article for an instruction on how to get this project work).
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Format: MS WORD
| Chapters: 1-5
| Pages: 50
ABSTRACT
In this project, two high performance adder cells are proposed. We simulated these two full adder cells using HSPICE in 0.18 µm, CMOS technology and at 25-degree of temperature with supply voltage range from 0.5v to 3.3v with 0.1v steps. Results show that the proposed adders operate successfully when connected to a 0.5 V power supply. The two adders differ in the technology applied to their gates. While the first circuit applies CMOS technology, the second and optimal one uses Past Transistor Logic. The average power dissipation of the optimum is 4.3269*10-7 watt, which illustrates an amazing performance. This paper demonstrates the PDP and Power Consumption of the proposed adders, and the comparison results among another six full adders.
In this project, two high performance adder cells are proposed. We simulated these two full adder cells using HSPICE in 0.18 µm, CMOS technology and at 25-degree of temperature with supply voltage range from 0.5v to 3.3v with 0.1v steps. Results show that the proposed adders operate successfully when connected to a 0.5 V power supply. The two adders differ in the technology applied to their gates. While the first circuit applies CMOS technology, the second and optimal one uses Past Transistor Logic. The average power dissipation of the optimum is 4.3269*10-7 watt, which illustrates an amazing performance. This paper demonstrates the PDP and Power Consumption of the proposed adders, and the comparison results among another six full adders.
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